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Integrated Quantum Frequency Processor Built on Silicon Chip

Researchers have fabricated a monolithic silicon quantum frequency processor integrating state generation, phase modulation, and pulse shaping on a single chip.

WHAT YOU NEED TO KNOW
  • The processor integrates a frequency comb source, pump-rejection filter, phase modulators, and pulse shaper on a 4 × 7 mm² silicon chip.
  • Tunable frequency beamsplitters demonstrated success probabilities exceeding 94% and fidelities above 99.9%.
  • On-chip frequency-bin quantum state tomography of a Bell-state achieved a fidelity of 95.7(3)%.

Researchers from the University of Pavia, CEA-Leti, and STMicroelectronics have demonstrated a fully integrated quantum frequency processor built entirely on a single silicon chip, according to a paper published in Nature Communications.

The platform relies on frequency-bin encoding, a photonic quantum architecture that offers high dimensionality and compatibility with existing telecommunications networks. Earlier deployments were restricted by the lack of a single platform capable of combining state generation, coherent frequency mixing, and programmable spectral control. The team addressed this restriction by unifying these functions on a 4 × 7 mm² silicon photonic chip.

Hardware integrated directly on the chip includes a microresonator-based biphoton quantum frequency comb source, a pump-rejection filter, high-speed phase modulators, and a four-channel line-by-line pulse shaper. These integrated elements allowed the team to generate and coherently manipulate high-dimensional frequency-bin entangled states without relying on off-chip optical routing.

Experimental tests demonstrated tunable frequency beamsplitters operating with success probabilities above 94% and fidelities exceeding 99.9%. The processor also synthesized single-qubit gates and directed two-photon quantum walks across the device. For state verification, the researchers performed on-chip frequency-bin quantum state tomography on an entangled Bell-state, recording a fidelity of 95.7(3)%.

The collaboration included researchers Sara Congia, Leopold Virot, Elena Rovetta, Matteo Galli, Massimo Borghi, Antonio Fincato, Frederic Boeuf, and Daniele Bajoni. CEA-Leti provided wafer-scale characterization and dicing, while funding came from the European Union’s STARLight and HyperSpace projects alongside Italy's PNRR MUR project NQSTI. The peer-reviewed paper was accepted on August 19, 2026, and published on September 15, 2026.

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